Gary Bist is a Staff Technical Writer at IBM's Toronto Lab.

Gary Bist是IBM多伦多实验室的专职技术作家。

Absrtact: Novel BIST scheme for SOC was presented in this paper.

摘要：文中提出了一种新颍的SOC芯片BIST方案。

In this thesis, we research on scan-based BIST techniques of digital systems.

本论文对数字系统基于扫描的BIST技术进行了深入研究。

SRAM BIST is also combined with ARM core's boundary scan testing during system level DFT.

系统级可测性设计主要是将存储器BIST与ARM核的边界扫描测试相结合。

The proposed BIST scheme relies on a pseudo-random testing phase and a deterministic phase.

这一自测试策略包含伪随机测试阶段和确定性测试阶段。

In this paper, the SOC design characteristics and mixed-mode testing of the BIST were discussed.

文中对SOC的设计特点及其BIST中的混合模式测试进行了探讨。

For the linear analog circuits, a BIST method based on the system's state variables is presented.

本文针对线性模拟电路，提出了一种基于系统状态变量的BIST方法。

The BIST structure circuit is simple and feasible, and the corresponding algorithm is easy to achieve.

电路结构简单可行，提供的相应算法也易于实现。

A new BIST structure with the method of test vector generation based on a controlled LFSR is proposed.

本文提出了一种基于受控线性反馈移位寄存器（LFSR）进行内建自测试的结构及其测试矢量生成方法。

BIST has been applied into transient current testing as an effective method to reduce testing spending.

内建自测试(BIST)是一种有效降低测试开销的技术，在瞬态电流测试中得到了应用。

Built-in self-test (BIST) is used as an effective test technique and it can greatly reduce test overheads.

内建自测试(BIST)作为一种有效的测试技术可以大大地降低测试开销。

Template is a cornerstone in the BIST for software, which affect the effectiveness and efficiency in software testing.

模板是软件内建自测试系统的基石，其内容关系到整个系统的性能和效果。

A partial scan algorithm for BIST, which combines the structure analysis and testability analysis, is presented in this paper.

提出了一种在内建自测试(BIST)中进行部分扫描的算法，此算法综合了电路的结构分析和可测性分析。

Conclusion The effect was same in two mode drainage after amend radical operation of mastocarcinoma. The single tract hold true bist...

结论乳癌改良根治术后两种负压引流的效果相同，单管负压引流适用于手术刀游离，双管负压引流适用于高频电刀游离。

The BIST controller can not only perform traditional memory test algorithms but also generates test patterns required for the logic part.

BIST控制器不仅可以执行传统的存储器测试算法，而且可以生成用于逻辑模块的测试向量。

The realizing principle and scheme of BIST are discussed in this paper. An example of BIST in digital display system of radar is demonstrated.

本文论述了系统自检的技术原理和实现方案，结合雷达显示系统给出了一个具体的例子。

Moreover, a scan test circuit was proposed. This circuit can implement scan test and high speed build in self test (BIST) for IP core chip tests.

另外，本文还针对IP核投片测试提出一种扫描测试电路结构，能够实现测试芯片的扫描测试和高速内建自测试(BIST)。

Aiming at the mixed-signal circuit testing, an integrated built-in self test (BIST) architecture for testing on-chip high speed ADC was presented.

针对混合信号电路的测试问题，提出了一种内建自测试(BIST)结构，分析并给出了如何利用该结构来计算片上高速模数转换器(adc)的静态参数。

Experimental results show that test velocity is K times faster than that of general BIST structure, while hardware cost is equivalent to that of general BIST.

实验结果表明，该方法的测试速度比一般BIST的速度快K倍(K为并行度)，而硬件花费与一般BIST结构相当。

The impacts of these problems were analyzed, and the corresponding solutions were presented, at the same time, a test technology combining with BIST was introduced.

分析了这些问题的影响，提出了相应措施，并介绍了结合BIST技术进行逻辑簇测试的方法。

The BIST of the principle of achieving is introduced first in this paper, then take the 8-bit ripple carry adder as an example, describes the design process of BIST.

文中首先介绍了内建自测试的实现原理，在此基础上以八位行波进位加法器为例，详细介绍了组合电路内建自测试的设计过程。

The top metal test pad, special test mode and BIST are adopted in the IC circuits to solve the IC test problem about the chip function test and electric character test.

通过添加测试引脚、设计专用测试模式，内建自测试等方法有效的解决了该芯片电路的功能测试和电气性能测试。

To reduce the storage volume of the test data during the built-in self-test (BIST), a new BIST technique based on two dimensional compression of test data is presented.

为压缩内建自测试(BIST)期间所需测试数据存储容量，提出了一种新的基于测试数据两维压缩的BIST方案。

For the test and verification of soft-IP, the paper presents a solution of Design For test technique, of which the BIST (Built-in Self test) is described in particular.

针对IP软核的测试、验证提出了面向测试、验证的IP软核设计方法—BIST内建自测试方法。

Using the BIST structure, we can calculate the static parameters of DAC's quickly, and improve the accuracy of testing which makes the circuit simple, compact and efficient.

利用该方法，既可以快速得到DAC的静态参数，又提高了测试精度，使得测试电路简单、紧凑和有效。

Based on the analysis of excessive power dissipation off ull-scan BIST, we present partial scan algorithm which selects a portion of registers for scan cells to implement low power BIST.

在分析全扫描内建自测试(BIST)过高测试功耗原因的基础上，提出了一种选择部分寄存器成为扫描单元的部分扫描算法来实现低功耗BIST。

Finally USES FPGA platform for BIST functions and timing verification, and through design compiler, static timing analysis, automatic placing and routing to achieve a BIST system layout.

最后利用FPGA平台实现了BIST的功能和时序验证，并通过综合、静态时序分析、自动布局布线实现了BIST系统的版图设计。

This article gives a new BIST test generator design for transient current testing, this design not only produces needed test vector pairs but also has an advantage of low hardware overheads.

本文给出了一种新型的瞬态电流测试BIST测试生成器设计方案，该设计可以产生所需要的测试向量对，同时具有硬件开销小的优点。

In order to reduce the storage requirements for the test patterns, a vertical and horizontal test data compression BIST scheme based on the test pattern generation of twisted-ring counter is proposed.

为了减少测试向量的存储需求，提出一种基于扭环计数器作为测试向量产生器的横向和竖向测试数据压缩的BIST方案。